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-rw-r--r--src/core/shader.c325
1 files changed, 154 insertions, 171 deletions
diff --git a/src/core/shader.c b/src/core/shader.c
index a508820..0490362 100644
--- a/src/core/shader.c
+++ b/src/core/shader.c
@@ -31,199 +31,182 @@ Vec4* reg_v4_03;
Vec4* reg_v4_04;
Vec4* reg_v4_05;
-Register reg_num[4] = {
- { 0, REGTYPE_NUM, NULL },
- { 0, REGTYPE_NUM, NULL },
- { 0, REGTYPE_NUM, NULL },
- { 0, REGTYPE_NUM, NULL },
+extern FragmentShaderIn ssr_frag_in;
+
+Register registers[REG_TOTAL] = {
+ /*4 float registers*/
+ { 0, REGTYPE_NUM, sizeof(float), NULL },
+ { 0, REGTYPE_NUM, sizeof(float), NULL },
+ { 0, REGTYPE_NUM, sizeof(float), NULL },
+ { 0, REGTYPE_NUM, sizeof(float), NULL },
+ /*6 vec2 registers*/
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ /*8 vec3 registers*/
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ /*6 vec4 registers*/
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL }
};
-Register reg_v2[6] = {
- { 0, REGTYPE_VEC2, NULL },
- { 0, REGTYPE_VEC2, NULL },
- { 0, REGTYPE_VEC2, NULL },
- { 0, REGTYPE_VEC2, NULL },
- { 0, REGTYPE_VEC2, NULL },
- { 0, REGTYPE_VEC2, NULL },
+ActiveReg active_regs[REG_TOTAL] = {
+ /*4 float registers*/
+ { sizeof(float), NULL, &reg_num_00, ssrS_bcpnum, &ssr_frag_in.num[0] },
+ { sizeof(float), NULL, &reg_num_01, ssrS_bcpnum, &ssr_frag_in.num[1] },
+ { sizeof(float), NULL, &reg_num_02, ssrS_bcpnum, &ssr_frag_in.num[2] },
+ { sizeof(float), NULL, &reg_num_03, ssrS_bcpnum, &ssr_frag_in.num[3] },
+ /*6 vec2 registers*/
+ { sizeof(Vec2), NULL, &reg_v2_00, ssrS_bcpvec2, &ssr_frag_in.v2[0] },
+ { sizeof(Vec2), NULL, &reg_v2_01, ssrS_bcpvec2, &ssr_frag_in.v2[1] },
+ { sizeof(Vec2), NULL, &reg_v2_02, ssrS_bcpvec2, &ssr_frag_in.v2[2] },
+ { sizeof(Vec2), NULL, &reg_v2_03, ssrS_bcpvec2, &ssr_frag_in.v2[3] },
+ { sizeof(Vec2), NULL, &reg_v2_04, ssrS_bcpvec2, &ssr_frag_in.v2[4] },
+ { sizeof(Vec2), NULL, &reg_v2_05, ssrS_bcpvec2, &ssr_frag_in.v2[5] },
+ /*8 vec3 registers*/
+ { sizeof(Vec3), NULL, &reg_v3_00, ssrS_bcpvec3, &ssr_frag_in.v3[0] },
+ { sizeof(Vec3), NULL, &reg_v3_01, ssrS_bcpvec3, &ssr_frag_in.v3[1] },
+ { sizeof(Vec3), NULL, &reg_v3_02, ssrS_bcpvec3, &ssr_frag_in.v3[2] },
+ { sizeof(Vec3), NULL, &reg_v3_03, ssrS_bcpvec3, &ssr_frag_in.v3[3] },
+ { sizeof(Vec3), NULL, &reg_v3_04, ssrS_bcpvec3, &ssr_frag_in.v3[4] },
+ { sizeof(Vec3), NULL, &reg_v3_05, ssrS_bcpvec3, &ssr_frag_in.v3[5] },
+ { sizeof(Vec3), NULL, &reg_v3_06, ssrS_bcpvec3, &ssr_frag_in.v3[6] },
+ { sizeof(Vec3), NULL, &reg_v3_07, ssrS_bcpvec3, &ssr_frag_in.v3[7] },
+ /*6 vec4 registers*/
+ { sizeof(Vec4), NULL, &reg_v4_00, ssrS_bcpvec4, &ssr_frag_in.v4[0] },
+ { sizeof(Vec4), NULL, &reg_v4_01, ssrS_bcpvec4, &ssr_frag_in.v4[1] },
+ { sizeof(Vec4), NULL, &reg_v4_02, ssrS_bcpvec4, &ssr_frag_in.v4[2] },
+ { sizeof(Vec4), NULL, &reg_v4_03, ssrS_bcpvec4, &ssr_frag_in.v4[3] },
+ { sizeof(Vec4), NULL, &reg_v4_04, ssrS_bcpvec4, &ssr_frag_in.v4[4] },
+ { sizeof(Vec4), NULL, &reg_v4_05, ssrS_bcpvec4, &ssr_frag_in.v4[5] }
};
-Register reg_v3[8] = {
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
- { 0, REGTYPE_VEC3, NULL },
-};
-
-Register reg_v4[6] = {
- { 0, REGTYPE_VEC4, NULL },
- { 0, REGTYPE_VEC4, NULL },
- { 0, REGTYPE_VEC4, NULL },
- { 0, REGTYPE_VEC4, NULL },
- { 0, REGTYPE_VEC4, NULL },
- { 0, REGTYPE_VEC4, NULL },
-};
-
-void ssrS_setregisters(uint flag, int capacity) {
-#define reg_scale_num(i) \
-if (flag & VARYING_NUM_##i) ssrM_rescalevector(float, reg_num[##i].num, reg_num[##i].length, capacity, FALSE)
-
-#define reg_scale_v2(i) \
-if (flag & VARYING_V2_##i) ssrM_rescalevector(Vec2, reg_v2[##i].v2, reg_v2[##i].length, capacity, FALSE)
-
-#define reg_scale_v3(i) \
-if (flag & VARYING_V3_##i) ssrM_rescalevector(Vec3, reg_v3[##i].v3, reg_v3[##i].length, capacity, FALSE)
-
-#define reg_scale_v4(i) \
-if (flag & VARYING_V4_##i) ssrM_rescalevector(Vec4, reg_v4[##i].v4, reg_v4[##i].length, capacity, FALSE)
-
- if (!(flag & VARYING_EXTRA))
+/*设置这个draw call开启的寄存器*/
+void ssrS_openregs(uint varying_flag) {
+ if (varying_flag & VARYING_EXTRA == 0)
+ {
+ open_regsi[0] = -1;
return;
-
- if (flag & VARYING_NUM) {
- reg_scale_num(00);
- reg_scale_num(01);
- reg_scale_num(02);
- reg_scale_num(03);
- }
- if (flag & VARYING_V2) {
- reg_scale_v2(00);
- reg_scale_v2(01);
- reg_scale_v2(02);
- reg_scale_v2(03);
- reg_scale_v2(04);
- reg_scale_v2(05);
}
- if (flag & VARYING_V3) {
- reg_scale_v3(00);
- reg_scale_v3(01);
- reg_scale_v3(02);
- reg_scale_v3(03);
- reg_scale_v3(04);
- reg_scale_v3(05);
- reg_scale_v3(06);
- reg_scale_v3(07);
- }
- if (flag & VARYING_V4) {
- reg_scale_v4(00);
- reg_scale_v4(01);
- reg_scale_v4(02);
- reg_scale_v4(03);
- reg_scale_v4(04);
- reg_scale_v4(05);
+ int j = 0;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ if (varying_flag & VARYING_EXTRA == 0)
+ break;
+ if (varying_flag & (1 << i)) {
+ open_regsi[j++] = i;
+ varying_flag &= ~(1 << i);
+ }
}
+ if(j < REG_TOTAL)
+ open_regsi[j] = -1;
}
-void ssrS_setupregisterpoints(uint extra_varying_flag, int idx) {
-#define set_reg_num_pointer(i)\
- if (extra_varying_flag & VARYING_NUM_##i) reg_num_##i = &reg_num[##i].num[idx];
-
-#define set_reg_v2_pointer(i)\
- if (extra_varying_flag & VARYING_V2_##i) reg_v2_##i = &reg_v2[##i].v2[idx];
-
-#define set_reg_v3_pointer(i)\
- if (extra_varying_flag & VARYING_V3_##i) reg_v3_##i = &reg_v3[##i].v3[idx];
-
-#define set_reg_v4_pointer(i)\
- if (extra_varying_flag & VARYING_V4_##i) reg_v4_##i = &reg_v4[##i].v4[idx];
-
- if (!(extra_varying_flag & VARYING_EXTRA))
- return;
- if (extra_varying_flag & VARYING_NUM) {
- set_reg_num_pointer(00);
- set_reg_num_pointer(01);
- set_reg_num_pointer(02);
- set_reg_num_pointer(03);
- }
- if (extra_varying_flag & VARYING_V2) {
- set_reg_v2_pointer(00);
- set_reg_v2_pointer(01);
- set_reg_v2_pointer(02);
- set_reg_v2_pointer(03);
- set_reg_v2_pointer(04);
- set_reg_v2_pointer(05);
- }
- if (extra_varying_flag & VARYING_V3) {
- set_reg_v3_pointer(00);
- set_reg_v3_pointer(01);
- set_reg_v3_pointer(02);
- set_reg_v3_pointer(03);
- set_reg_v3_pointer(04);
- set_reg_v3_pointer(05);
- set_reg_v3_pointer(06);
- set_reg_v3_pointer(07);
- }
- if (extra_varying_flag & VARYING_V4) {
- set_reg_v4_pointer(00);
- set_reg_v4_pointer(01);
- set_reg_v4_pointer(02);
- set_reg_v4_pointer(03);
- set_reg_v4_pointer(04);
- set_reg_v4_pointer(05);
+void ssrS_setactiveregr() { /*set active reg data from registers*/
+ int index = 0;
+ ActiveReg* reg;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ reg->data = registers[index].data;
}
}
-void ssrS_setregtofragin(uint extra_varying_flag, FragmentShaderIn* frag_in){
-#define set_reg_num_pointer_to_fragin(i)\
- if (extra_varying_flag & VARYING_NUM_##i) reg_num_##i = &frag_in->num[##i];
+extern byte* clip_buffer_data[REG_TOTAL];
-#define set_reg_v2_pointer_to_fragin(i)\
- if (extra_varying_flag & VARYING_V2_##i) reg_v2_##i = &frag_in->v2[##i];
-
-#define set_reg_v3_pointer_to_fragin(i)\
- if (extra_varying_flag & VARYING_V3_##i) reg_v3_##i = &frag_in->v3[##i];
-
-#define set_reg_v4_pointer_to_fragin(i)\
- if (extra_varying_flag & VARYING_V4_##i) reg_v4_##i = &frag_in->v4[##i];
-
- if (!(extra_varying_flag & VARYING_EXTRA))
- return;
- if (extra_varying_flag & VARYING_NUM) {
- set_reg_num_pointer_to_fragin(00);
- set_reg_num_pointer_to_fragin(01);
- set_reg_num_pointer_to_fragin(02);
- set_reg_num_pointer_to_fragin(03);
+void ssrS_setactiveregc() { /*set active reg data from clipping buffer*/
+ int index = 0;
+ ActiveReg* reg;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ reg->data = clip_buffer_data[index];
}
- if (extra_varying_flag & VARYING_V2) {
- set_reg_v2_pointer_to_fragin(00);
- set_reg_v2_pointer_to_fragin(01);
- set_reg_v2_pointer_to_fragin(02);
- set_reg_v2_pointer_to_fragin(03);
- set_reg_v2_pointer_to_fragin(04);
- set_reg_v2_pointer_to_fragin(05);
+}
+
+/*计算寄存器中的值并输出*/
+void ssrS_solveregs(Vec3* bc, uint a, uint b, uint c) {
+ int index = 0;
+ uint stride = 0;
+ ActiveReg* reg;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ stride = reg->element_size;
+ reg->accessor = reg->bcp_interpolator(
+ bc
+ , &reg->data[a*stride]
+ , &reg->data[b*stride]
+ , &reg->data[c*stride]
+ , reg->output
+ );
}
- if (extra_varying_flag & VARYING_V3) {
- set_reg_v3_pointer_to_fragin(00);
- set_reg_v3_pointer_to_fragin(01);
- set_reg_v3_pointer_to_fragin(02);
- set_reg_v3_pointer_to_fragin(03);
- set_reg_v3_pointer_to_fragin(04);
- set_reg_v3_pointer_to_fragin(05);
- set_reg_v3_pointer_to_fragin(06);
- set_reg_v3_pointer_to_fragin(07);
+}
+
+/*给寄存器扩容（如果需要的话）*/
+void ssrS_setregisters(int capacity) {
+ Register* reg;
+ byte* data;
+ uint index;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &registers[index];
+ data = reg->data;
+ if (reg->length >= capacity)
+ continue;
+ if (!data)
+ data = (byte*)calloc(capacity * reg->element_size, sizeof(byte));
+ else
+ data = (byte*)realloc(data, capacity * reg->element_size);
+ reg->data = data;
+ reg->length = capacity;
}
- if (extra_varying_flag & VARYING_V4) {
- set_reg_v4_pointer_to_fragin(00);
- set_reg_v4_pointer_to_fragin(01);
- set_reg_v4_pointer_to_fragin(02);
- set_reg_v4_pointer_to_fragin(03);
- set_reg_v4_pointer_to_fragin(04);
- set_reg_v4_pointer_to_fragin(05);
+}
+
+/*进入vert shader前设置寄存器指针到对应顶点的数据在寄存器中的位置*/
+void ssrS_setupregisterpoints(int idx) {
+ ActiveReg* reg;
+ uint index;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ *reg->accessor = &reg->data[idx * reg->element_size];
}
}
-Color32 texture2d(Texture* tex, Vec2* uv) {
- FilterMode filter_mode = ssr_getfiltermode();
- WrapMode wrap_mode = ssr_getwrapmode();
- return texture_sampling(tex, filter_mode, wrap_mode, uv->x, uv->y);
+/*进入frag shader前，将寄存器指针设置到fragment-in对应的位置*/
+void ssrS_setregtofragin() {
+ ActiveReg* reg;
+ uint index;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ *reg->accessor = reg->output;
+ }
}
-float* ssrS_bcpnum(Vec3* bc, float A, float B, float C, float* out) {
+float* ssrS_bcpnum(Vec3* bc, float* A, float* B, float* C, float* out) {
ssr_assert(bc && out);
- *out = bc->A * A + bc->B * B + bc->C * C;
+ *out = bc->A * *A + bc->B * *B + bc->C * *C;
return out;
}
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