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Diffstat (limited to 'src/core/shader.c')
-rw-r--r--src/core/shader.c80
1 files changed, 52 insertions, 28 deletions
diff --git a/src/core/shader.c b/src/core/shader.c
index 86c2ad6..d7ef26f 100644
--- a/src/core/shader.c
+++ b/src/core/shader.c
@@ -14,6 +14,8 @@ Vec2* reg_v2_02;
Vec2* reg_v2_03;
Vec2* reg_v2_04;
Vec2* reg_v2_05;
+Vec2* reg_v2_06;
+Vec2* reg_v2_07;
Vec3* reg_v3_00;
Vec3* reg_v3_01;
@@ -23,6 +25,10 @@ Vec3* reg_v3_04;
Vec3* reg_v3_05;
Vec3* reg_v3_06;
Vec3* reg_v3_07;
+Vec3* reg_v3_08;
+Vec3* reg_v3_09;
+Vec3* reg_v3_10;
+Vec3* reg_v3_11;
Vec4* reg_v4_00;
Vec4* reg_v4_01;
@@ -30,6 +36,8 @@ Vec4* reg_v4_02;
Vec4* reg_v4_03;
Vec4* reg_v4_04;
Vec4* reg_v4_05;
+Vec4* reg_v4_06;
+Vec4* reg_v4_07;
extern FragmentShaderIn ssr_frag_in;
@@ -39,14 +47,18 @@ Register registers[REG_TOTAL] = {
{ 0, REGTYPE_NUM, sizeof(float), NULL },
{ 0, REGTYPE_NUM, sizeof(float), NULL },
{ 0, REGTYPE_NUM, sizeof(float), NULL },
- /*6 vec2 registers*/
+ /*8 vec2 registers*/
{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
- /*8 vec3 registers*/
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ { 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
+ /*12 vec3 registers*/
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
@@ -55,7 +67,11 @@ Register registers[REG_TOTAL] = {
{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
- /*6 vec4 registers*/
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ { 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
+ /*8 vec4 registers*/
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
+ { 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
@@ -70,14 +86,16 @@ ActiveReg active_regs[REG_TOTAL] = {
{ sizeof(float), NULL, &reg_num_01, ssrS_bcpnum, &ssr_frag_in.num[1] },
{ sizeof(float), NULL, &reg_num_02, ssrS_bcpnum, &ssr_frag_in.num[2] },
{ sizeof(float), NULL, &reg_num_03, ssrS_bcpnum, &ssr_frag_in.num[3] },
- /*6 vec2 registers*/
+ /*8 vec2 registers*/
{ sizeof(Vec2), NULL, &reg_v2_00, ssrS_bcpvec2, &ssr_frag_in.v2[0] },
{ sizeof(Vec2), NULL, &reg_v2_01, ssrS_bcpvec2, &ssr_frag_in.v2[1] },
{ sizeof(Vec2), NULL, &reg_v2_02, ssrS_bcpvec2, &ssr_frag_in.v2[2] },
{ sizeof(Vec2), NULL, &reg_v2_03, ssrS_bcpvec2, &ssr_frag_in.v2[3] },
{ sizeof(Vec2), NULL, &reg_v2_04, ssrS_bcpvec2, &ssr_frag_in.v2[4] },
{ sizeof(Vec2), NULL, &reg_v2_05, ssrS_bcpvec2, &ssr_frag_in.v2[5] },
- /*8 vec3 registers*/
+ { sizeof(Vec2), NULL, &reg_v2_06, ssrS_bcpvec2, &ssr_frag_in.v2[6] },
+ { sizeof(Vec2), NULL, &reg_v2_07, ssrS_bcpvec2, &ssr_frag_in.v2[7] },
+ /*12 vec3 registers*/
{ sizeof(Vec3), NULL, &reg_v3_00, ssrS_bcpvec3, &ssr_frag_in.v3[0] },
{ sizeof(Vec3), NULL, &reg_v3_01, ssrS_bcpvec3, &ssr_frag_in.v3[1] },
{ sizeof(Vec3), NULL, &reg_v3_02, ssrS_bcpvec3, &ssr_frag_in.v3[2] },
@@ -86,42 +104,48 @@ ActiveReg active_regs[REG_TOTAL] = {
{ sizeof(Vec3), NULL, &reg_v3_05, ssrS_bcpvec3, &ssr_frag_in.v3[5] },
{ sizeof(Vec3), NULL, &reg_v3_06, ssrS_bcpvec3, &ssr_frag_in.v3[6] },
{ sizeof(Vec3), NULL, &reg_v3_07, ssrS_bcpvec3, &ssr_frag_in.v3[7] },
- /*6 vec4 registers*/
+ { sizeof(Vec3), NULL, &reg_v3_08, ssrS_bcpvec3, &ssr_frag_in.v3[8] },
+ { sizeof(Vec3), NULL, &reg_v3_09, ssrS_bcpvec3, &ssr_frag_in.v3[9] },
+ { sizeof(Vec3), NULL, &reg_v3_10, ssrS_bcpvec3, &ssr_frag_in.v3[10] },
+ { sizeof(Vec3), NULL, &reg_v3_11, ssrS_bcpvec3, &ssr_frag_in.v3[11] },
+ /*8 vec4 registers*/
{ sizeof(Vec4), NULL, &reg_v4_00, ssrS_bcpvec4, &ssr_frag_in.v4[0] },
{ sizeof(Vec4), NULL, &reg_v4_01, ssrS_bcpvec4, &ssr_frag_in.v4[1] },
{ sizeof(Vec4), NULL, &reg_v4_02, ssrS_bcpvec4, &ssr_frag_in.v4[2] },
{ sizeof(Vec4), NULL, &reg_v4_03, ssrS_bcpvec4, &ssr_frag_in.v4[3] },
{ sizeof(Vec4), NULL, &reg_v4_04, ssrS_bcpvec4, &ssr_frag_in.v4[4] },
- { sizeof(Vec4), NULL, &reg_v4_05, ssrS_bcpvec4, &ssr_frag_in.v4[5] }
+ { sizeof(Vec4), NULL, &reg_v4_05, ssrS_bcpvec4, &ssr_frag_in.v4[5] },
+ { sizeof(Vec4), NULL, &reg_v4_06, ssrS_bcpvec4, &ssr_frag_in.v4[6] },
+ { sizeof(Vec4), NULL, &reg_v4_07, ssrS_bcpvec4, &ssr_frag_in.v4[7] },
};
/*设置这个draw call开启的寄存器*/
void ssrS_openregs(uint varying_flag) {
- if (varying_flag & VARYING_EXTRA == 0)
+ if (varying_flag & VARYING_ANY == 0)
{
open_regsi[0] = -1;
return;
}
int j = 0;
for (int i = 0; i < REG_TOTAL; ++i) {
- if (varying_flag & VARYING_EXTRA == 0)
+ if (varying_flag & VARYING_ANY == 0)
break;
if (varying_flag & (1 << i)) {
open_regsi[j++] = i;
varying_flag &= ~(1 << i);
}
}
- if(j < REG_TOTAL)
+ if (j < REG_TOTAL)
open_regsi[j] = -1;
}
void ssrS_setactiveregr() { /*set active reg data from registers*/
int index = 0;
- ActiveReg* reg;
+ ActiveReg* reg;
for (int i = 0; i < REG_TOTAL; ++i) {
index = open_regsi[i];
- if (index == -1) break;
- reg = &active_regs[index];
+ if (index == -1) break;
+ reg = &active_regs[index];
reg->data = registers[index].data;
}
}
@@ -160,19 +184,19 @@ void ssrS_solveregs(Vec3* bc, uint a, uint b, uint c) {
}
/*计算基础属性的插值，并输出*/
-void ssrS_solveprops(uint varying_flag, Vec3* bc, Vert* A, Vert* B, Vert* C) {
- if (varying_flag & VARYING_BASIC) {
- if (varying_flag & VARYING_POSITION) ssrS_bcpvec3(bc, &A->position, &B->position, &C->position, &ssr_frag_in.position);
- if (varying_flag & VARYING_NORMAL) ssrS_bcpvec3(bc, &A->normal, &B->normal, &C->normal, &ssr_frag_in.normal);
- if (varying_flag & VARYING_TANGENT) ssrS_bcpvec3(bc, &A->tangent, &B->tangent, &C->tangent, &ssr_frag_in.tangent);
- if (varying_flag & VARYING_TEXCOORD) ssrS_bcpvec2(bc, &A->texcoord, &B->texcoord, &C->texcoord, &ssr_frag_in.texcoord);
-/*
- if (varying_flag & VARYING_JOINT) ssrS_bcpvec4(&bc, &A->joint, &B->joint, &C->joint, &ssr_frag_in.joint);
- if (varying_flag & VARYING_WEIGHT) ssrS_bcpvec4(&bc, &A->weight, &B->weight, &C->weight, &ssr_frag_in.weight);
-*/
- if (varying_flag & VARYING_COLOR) ssrS_bcpcolor(bc, A->color, B->color, C->color, &ssr_frag_in.color);
- }
-}
+//void ssrS_solveprops(uint varying_flag, Vec3* bc, Vert* A, Vert* B, Vert* C) {
+// if (varying_flag & VARYING_BASIC) {
+// if (varying_flag & VARYING_POSITION) ssrS_bcpvec3(bc, &A->position, &B->position, &C->position, &ssr_frag_in.position);
+// if (varying_flag & VARYING_NORMAL) ssrS_bcpvec3(bc, &A->normal, &B->normal, &C->normal, &ssr_frag_in.normal);
+// if (varying_flag & VARYING_TANGENT) ssrS_bcpvec3(bc, &A->tangent, &B->tangent, &C->tangent, &ssr_frag_in.tangent);
+// if (varying_flag & VARYING_TEXCOORD) ssrS_bcpvec2(bc, &A->texcoord, &B->texcoord, &C->texcoord, &ssr_frag_in.texcoord);
+// /*
+// if (varying_flag & VARYING_JOINT) ssrS_bcpvec4(&bc, &A->joint, &B->joint, &C->joint, &ssr_frag_in.joint);
+// if (varying_flag & VARYING_WEIGHT) ssrS_bcpvec4(&bc, &A->weight, &B->weight, &C->weight, &ssr_frag_in.weight);
+// */
+// if (varying_flag & VARYING_COLOR) ssrS_bcpcolor(bc, A->color, B->color, C->color, &ssr_frag_in.color);
+// }
+//}
/*给寄存器扩容（如果需要的话）*/
void ssrS_setregisters(int capacity) {
@@ -185,7 +209,7 @@ void ssrS_setregisters(int capacity) {
reg = &registers[index];
data = reg->data;
if (reg->length >= capacity)
- continue;
+ continue;
if (!data)
data = (byte*)calloc(capacity * reg->element_size, sizeof(byte));
else
@@ -197,7 +221,7 @@ void ssrS_setregisters(int capacity) {
/*进入vert shader前设置寄存器指针到对应顶点的数据在寄存器中的位置*/
void ssrS_setupregisterpoints(int idx) {
- ActiveReg* reg;
+ ActiveReg* reg;
uint index;
for (int i = 0; i < REG_TOTAL; ++i) {
index = open_regsi[i];
generated by cgit v1.1-26-g67d0 at 2025-05-18 17:56:27 +0000