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-rw-r--r--src/core/shader.c104
1 files changed, 69 insertions, 35 deletions
diff --git a/src/core/shader.c b/src/core/shader.c
index b28a5e2..899a160 100644
--- a/src/core/shader.c
+++ b/src/core/shader.c
@@ -46,41 +46,41 @@ Register registers[REG_TOTAL] = {
ActiveReg active_regs[REG_TOTAL] = {
/*4 float registers*/
- { sizeof(float), NULL, &reg_num_00, ssrS_bcpnum, &ssr_frag_in.num[0] },
- { sizeof(float), NULL, &reg_num_01, ssrS_bcpnum, &ssr_frag_in.num[1] },
- { sizeof(float), NULL, &reg_num_02, ssrS_bcpnum, &ssr_frag_in.num[2] },
- { sizeof(float), NULL, &reg_num_03, ssrS_bcpnum, &ssr_frag_in.num[3] },
- /*8 vec2 registers*/
- { sizeof(Vec2), NULL, &reg_v2_00, ssrS_bcpvec2, &ssr_frag_in.v2[0] },
- { sizeof(Vec2), NULL, &reg_v2_01, ssrS_bcpvec2, &ssr_frag_in.v2[1] },
- { sizeof(Vec2), NULL, &reg_v2_02, ssrS_bcpvec2, &ssr_frag_in.v2[2] },
- { sizeof(Vec2), NULL, &reg_v2_03, ssrS_bcpvec2, &ssr_frag_in.v2[3] },
- { sizeof(Vec2), NULL, &reg_v2_04, ssrS_bcpvec2, &ssr_frag_in.v2[4] },
- { sizeof(Vec2), NULL, &reg_v2_05, ssrS_bcpvec2, &ssr_frag_in.v2[5] },
- { sizeof(Vec2), NULL, &reg_v2_06, ssrS_bcpvec2, &ssr_frag_in.v2[6] },
- { sizeof(Vec2), NULL, &reg_v2_07, ssrS_bcpvec2, &ssr_frag_in.v2[7] },
+ { sizeof(float), NULL, &reg_num_00, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[0] },
+ { sizeof(float), NULL, &reg_num_01, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[1] },
+ { sizeof(float), NULL, &reg_num_02, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[2] },
+ { sizeof(float), NULL, &reg_num_03, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[3] },
+ /*8 vec2 registers*/
+ { sizeof(Vec2), NULL, &reg_v2_00, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[0] },
+ { sizeof(Vec2), NULL, &reg_v2_01, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[1] },
+ { sizeof(Vec2), NULL, &reg_v2_02, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[2] },
+ { sizeof(Vec2), NULL, &reg_v2_03, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[3] },
+ { sizeof(Vec2), NULL, &reg_v2_04, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[4] },
+ { sizeof(Vec2), NULL, &reg_v2_05, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[5] },
+ { sizeof(Vec2), NULL, &reg_v2_06, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[6] },
+ { sizeof(Vec2), NULL, &reg_v2_07, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[7] },
/*12 vec3 registers*/
- { sizeof(Vec3), NULL, &reg_v3_00, ssrS_bcpvec3, &ssr_frag_in.v3[0] },
- { sizeof(Vec3), NULL, &reg_v3_01, ssrS_bcpvec3, &ssr_frag_in.v3[1] },
- { sizeof(Vec3), NULL, &reg_v3_02, ssrS_bcpvec3, &ssr_frag_in.v3[2] },
- { sizeof(Vec3), NULL, &reg_v3_03, ssrS_bcpvec3, &ssr_frag_in.v3[3] },
- { sizeof(Vec3), NULL, &reg_v3_04, ssrS_bcpvec3, &ssr_frag_in.v3[4] },
- { sizeof(Vec3), NULL, &reg_v3_05, ssrS_bcpvec3, &ssr_frag_in.v3[5] },
- { sizeof(Vec3), NULL, &reg_v3_06, ssrS_bcpvec3, &ssr_frag_in.v3[6] },
- { sizeof(Vec3), NULL, &reg_v3_07, ssrS_bcpvec3, &ssr_frag_in.v3[7] },
- { sizeof(Vec3), NULL, &reg_v3_08, ssrS_bcpvec3, &ssr_frag_in.v3[8] },
- { sizeof(Vec3), NULL, &reg_v3_09, ssrS_bcpvec3, &ssr_frag_in.v3[9] },
- { sizeof(Vec3), NULL, &reg_v3_10, ssrS_bcpvec3, &ssr_frag_in.v3[10] },
- { sizeof(Vec3), NULL, &reg_v3_11, ssrS_bcpvec3, &ssr_frag_in.v3[11] },
+ { sizeof(Vec3), NULL, &reg_v3_00, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[0] },
+ { sizeof(Vec3), NULL, &reg_v3_01, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[1] },
+ { sizeof(Vec3), NULL, &reg_v3_02, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[2] },
+ { sizeof(Vec3), NULL, &reg_v3_03, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[3] },
+ { sizeof(Vec3), NULL, &reg_v3_04, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[4] },
+ { sizeof(Vec3), NULL, &reg_v3_05, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[5] },
+ { sizeof(Vec3), NULL, &reg_v3_06, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[6] },
+ { sizeof(Vec3), NULL, &reg_v3_07, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[7] },
+ { sizeof(Vec3), NULL, &reg_v3_08, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[8] },
+ { sizeof(Vec3), NULL, &reg_v3_09, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[9] },
+ { sizeof(Vec3), NULL, &reg_v3_10, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[10] },
+ { sizeof(Vec3), NULL, &reg_v3_11, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[11] },
/*8 vec4 registers*/
- { sizeof(Vec4), NULL, &reg_v4_00, ssrS_bcpvec4, &ssr_frag_in.v4[0] },
- { sizeof(Vec4), NULL, &reg_v4_01, ssrS_bcpvec4, &ssr_frag_in.v4[1] },
- { sizeof(Vec4), NULL, &reg_v4_02, ssrS_bcpvec4, &ssr_frag_in.v4[2] },
- { sizeof(Vec4), NULL, &reg_v4_03, ssrS_bcpvec4, &ssr_frag_in.v4[3] },
- { sizeof(Vec4), NULL, &reg_v4_04, ssrS_bcpvec4, &ssr_frag_in.v4[4] },
- { sizeof(Vec4), NULL, &reg_v4_05, ssrS_bcpvec4, &ssr_frag_in.v4[5] },
- { sizeof(Vec4), NULL, &reg_v4_06, ssrS_bcpvec4, &ssr_frag_in.v4[6] },
- { sizeof(Vec4), NULL, &reg_v4_07, ssrS_bcpvec4, &ssr_frag_in.v4[7] },
+ { sizeof(Vec4), NULL, &reg_v4_00, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[0] },
+ { sizeof(Vec4), NULL, &reg_v4_01, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[1] },
+ { sizeof(Vec4), NULL, &reg_v4_02, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[2] },
+ { sizeof(Vec4), NULL, &reg_v4_03, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[3] },
+ { sizeof(Vec4), NULL, &reg_v4_04, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[4] },
+ { sizeof(Vec4), NULL, &reg_v4_05, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[5] },
+ { sizeof(Vec4), NULL, &reg_v4_06, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[6] },
+ { sizeof(Vec4), NULL, &reg_v4_07, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[7] },
};
/*设置这个draw call开启的寄存器*/
@@ -127,8 +127,8 @@ void ssrS_setactiveregc() { /*set active reg data from clipping buffer*/
}
}
-/*计算寄存器中的值并输出*/
-void ssrS_solveregs(Vec3* bc, uint ia, uint ib, uint ic) {
+/*用重心插值计算寄存器中的值并输出*/
+void ssrS_solveregsbcp(Vec3* bc, uint ia, uint ib, uint ic) {
int index = 0;
uint stride = 0;
ActiveReg* reg;
@@ -147,6 +147,40 @@ void ssrS_solveregs(Vec3* bc, uint ia, uint ib, uint ic) {
}
}
+/*用线性插值计算寄存器中的值并输出*/
+void ssrS_solveregslerp(float t, uint ia, uint ib) {
+ int index = 0;
+ uint stride = 0;
+ ActiveReg* reg;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ stride = reg->element_size;
+ *reg->accessor = reg->linear_interpolator(
+ t
+ , &reg->data[ia*stride]
+ , &reg->data[ib*stride]
+ , reg->output
+ );
+ }
+}
+
+/*绘制点图元的时候直接拷贝不需要线性插值*/
+void ssrS_solveregscopy(uint pindex) {
+ int index = 0;
+ uint stride = 0;
+ ActiveReg* reg;
+ for (int i = 0; i < REG_TOTAL; ++i) {
+ index = open_regsi[i];
+ if (index == -1) break;
+ reg = &active_regs[index];
+ stride = reg->element_size;
+ ssrM_copy(reg->output, &reg->data[pindex*stride], stride);
+ *reg->accessor = reg->output;
+ }
+}
+
/*给寄存器扩容（如果需要的话）*/
void ssrS_setregisters(int capacity) {
Register* reg;
generated by cgit v1.1-26-g67d0 at 2025-05-18 20:44:11 +0000