path: root/src/core/shader.c

#include "../math/math.h"
#include "shader.h"
#include "vert.h"
#include "device.h"

extern FragmentShaderIn ssr_frag_in;

Register registers[REG_TOTAL] = {
	/*4 float registers*/
	{ 0, REGTYPE_NUM, sizeof(float), NULL },
	{ 0, REGTYPE_NUM, sizeof(float), NULL },
	{ 0, REGTYPE_NUM, sizeof(float), NULL },
	{ 0, REGTYPE_NUM, sizeof(float), NULL },
	/*8 vec2 registers*/
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	{ 0, REGTYPE_VEC2, sizeof(Vec2), NULL },
	/*12 vec3 registers*/
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	{ 0, REGTYPE_VEC3, sizeof(Vec3), NULL },
	/*8 vec4 registers*/
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL },
	{ 0, REGTYPE_VEC4, sizeof(Vec4), NULL }
};

ActiveReg active_regs[REG_TOTAL] = {
	/*4 float registers*/
	{ sizeof(float), NULL, &reg_num_00, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[0] },
	{ sizeof(float), NULL, &reg_num_01, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[1] },
	{ sizeof(float), NULL, &reg_num_02, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[2] },
	{ sizeof(float), NULL, &reg_num_03, ssrS_bcpnum, ssrS_lerpnum, &ssr_frag_in.num[3] },
	/*8 vec2 registers*/														 
	{ sizeof(Vec2), NULL, &reg_v2_00, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[0] },
	{ sizeof(Vec2), NULL, &reg_v2_01, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[1] },
	{ sizeof(Vec2), NULL, &reg_v2_02, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[2] },
	{ sizeof(Vec2), NULL, &reg_v2_03, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[3] },
	{ sizeof(Vec2), NULL, &reg_v2_04, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[4] },
	{ sizeof(Vec2), NULL, &reg_v2_05, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[5] },
	{ sizeof(Vec2), NULL, &reg_v2_06, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[6] },
	{ sizeof(Vec2), NULL, &reg_v2_07, ssrS_bcpvec2, ssrS_lerpvec2, &ssr_frag_in.v2[7] },
	/*12 vec3 registers*/
	{ sizeof(Vec3), NULL, &reg_v3_00, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[0] },
	{ sizeof(Vec3), NULL, &reg_v3_01, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[1] },
	{ sizeof(Vec3), NULL, &reg_v3_02, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[2] },
	{ sizeof(Vec3), NULL, &reg_v3_03, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[3] },
	{ sizeof(Vec3), NULL, &reg_v3_04, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[4] },
	{ sizeof(Vec3), NULL, &reg_v3_05, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[5] },
	{ sizeof(Vec3), NULL, &reg_v3_06, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[6] },
	{ sizeof(Vec3), NULL, &reg_v3_07, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[7] },
	{ sizeof(Vec3), NULL, &reg_v3_08, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[8] },
	{ sizeof(Vec3), NULL, &reg_v3_09, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[9] },
	{ sizeof(Vec3), NULL, &reg_v3_10, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[10] },
	{ sizeof(Vec3), NULL, &reg_v3_11, ssrS_bcpvec3, ssrS_lerpvec3, &ssr_frag_in.v3[11] },
	/*8 vec4 registers*/
	{ sizeof(Vec4), NULL, &reg_v4_00, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[0] },
	{ sizeof(Vec4), NULL, &reg_v4_01, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[1] },
	{ sizeof(Vec4), NULL, &reg_v4_02, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[2] },
	{ sizeof(Vec4), NULL, &reg_v4_03, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[3] },
	{ sizeof(Vec4), NULL, &reg_v4_04, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[4] },
	{ sizeof(Vec4), NULL, &reg_v4_05, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[5] },
	{ sizeof(Vec4), NULL, &reg_v4_06, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[6] },
	{ sizeof(Vec4), NULL, &reg_v4_07, ssrS_bcpvec4, ssrS_lerpvec4, &ssr_frag_in.v4[7] },
};

/*设置这个draw call开启的寄存器*/
void ssrS_openregs(uint varying_flag) {
	if (varying_flag & VARYING_ANY == 0)
	{
		open_regsi[0] = -1;
		return;
	}
	int j = 0;
	for (int i = 0; i < REG_TOTAL; ++i) {
		if (varying_flag & VARYING_ANY == 0)
			break;
		if (varying_flag & (1 << i)) {
			open_regsi[j++] = i;
			varying_flag &= ~(1 << i);
		}
	}
	if (j < REG_TOTAL)
		open_regsi[j] = -1;
}

void ssrS_setactiveregr() { /*set active reg data from registers*/
	int regi = 0;
	ActiveReg* reg;
	for (int i = 0; i < REG_TOTAL; ++i) {
		regi = open_regsi[i];
		if (regi == -1) break;
		reg = &active_regs[regi];
		reg->data = registers[regi].data;
	}
}

extern byte* clip_buffer_data[REG_TOTAL];

void ssrS_setactiveregc() { /*set active reg data from clipping buffer*/
	int regi = 0;
	ActiveReg* reg;
	for (int i = 0; i < REG_TOTAL; ++i) {
		regi = open_regsi[i];
		if (regi == -1) break;
		reg = &active_regs[regi];
		reg->data = clip_buffer_data[regi];
	}
}

/*用重心插值计算寄存器中的值并输出*/
void ssrS_solveregsbcp(Vec3* bc, uint ia, uint ib, uint ic) {
	int index = 0;
	uint stride = 0;
	ActiveReg* reg;
	for (int i = 0; i < REG_TOTAL; ++i) {
		index = open_regsi[i];
		if (index == -1) break;
		reg = &active_regs[index];
		stride = reg->element_size;
		*reg->accessor = reg->bcp_interpolator(
			bc
			, &reg->data[ia*stride]
			, &reg->data[ib*stride]
			, &reg->data[ic*stride]
			, reg->output
		);
	}
}

/*用线性插值计算寄存器中的值并输出*/
void ssrS_solveregslerp(float t, uint ia, uint ib) {
	int index = 0;
	uint stride = 0;
	ActiveReg* reg;
	for (int i = 0; i < REG_TOTAL; ++i) {
		index = open_regsi[i];
		if (index == -1) break;
		reg = &active_regs[index];
		stride = reg->element_size;
		*reg->accessor = reg->linear_interpolator(
			t
			, &reg->data[ia*stride]
			, &reg->data[ib*stride]
			, reg->output
		);
	}
}

/*绘制点图元的时候直接拷贝不需要线性插值*/
void ssrS_solveregscopy(uint pindex) {
	int index = 0;
	uint stride = 0;
	ActiveReg* reg;
	for (int i = 0; i < REG_TOTAL; ++i) {
		index = open_regsi[i];
		if (index == -1) break;
		reg = &active_regs[index];
		stride = reg->element_size;
		ssrM_copy(reg->output, &reg->data[pindex*stride], stride);
		*reg->accessor = reg->output;
	}
}

/*给寄存器扩容（如果需要的话）*/
void ssrS_setregisters(int capacity) {
	Register* reg;
	byte* data;
	uint index;
	for (int i = 0; i < REG_TOTAL; ++i) {
		index = open_regsi[i];
		if (index == -1) break;
		reg = &registers[index];
		data = reg->data;
		if (reg->length >= capacity)
			continue;
		if (!data)
			data = (byte*)calloc(capacity * reg->element_size, sizeof(byte));
		else
			data = (byte*)realloc(data, capacity * reg->element_size);
		reg->data = data;
		reg->length = capacity;
	}
}

/*进入vert shader前设置寄存器指针到对应顶点的数据在寄存器中的位置*/
void ssrS_setupregisterpointers(int idx) {
	ActiveReg* reg;
	uint index;
	for (int i = 0; i < REG_TOTAL; ++i) {
		index = open_regsi[i];
		if (index == -1) break;
		reg = &active_regs[index];
		*reg->accessor = &reg->data[idx * reg->element_size];
	}
}

/*进入frag shader前，将寄存器指针设置到fragment-in对应的位置*/
void ssrS_setregtofragin() {
	ActiveReg* reg;
	uint index;
	for (int i = 0; i < REG_TOTAL; ++i) {
		index = open_regsi[i];
		if (index == -1) break;
		reg = &active_regs[index];
		*reg->accessor = reg->output;
	}
}

float* ssrS_bcpnum(Vec3* bc, float* A, float* B, float* C, float* out) {
	ssr_assert(bc && out);
	*out = bc->A * *A + bc->B * *B + bc->C * *C;
	return out;
}

Color* ssrS_bcpcolor(Vec3* bc, Color A, Color B, Color C, Color* out) {
	ssr_assert(bc && out);
	*out = ssr_color(
		bc->A * COLOR_R(A) + bc->B * COLOR_R(B) + bc->C * COLOR_R(C),
		bc->A * COLOR_G(A) + bc->B * COLOR_G(B) + bc->C * COLOR_G(C),
		bc->A * COLOR_B(A) + bc->B * COLOR_B(B) + bc->C * COLOR_B(C),
		bc->A * COLOR_A(A) + bc->B * COLOR_A(B) + bc->C * COLOR_A(C)
	);
	return out;
}

Vec2* ssrS_bcpvec2(Vec3* bc, Vec2* A, Vec2* B, Vec2* C, Vec2* out) {
	ssr_assert(bc && A && B && C && out);
	out->x = bc->A * A->x + bc->B * B->x + bc->C * C->x;
	out->y = bc->A * A->y + bc->B * B->y + bc->C * C->y;
	return out;
}

Vec3* ssrS_bcpvec3(Vec3* bc, Vec3* A, Vec3* B, Vec3* C, Vec3* out) {
	ssr_assert(bc && A && B && C && out);
	out->x = bc->A * A->x + bc->B * B->x + bc->C * C->x;
	out->y = bc->A * A->y + bc->B * B->y + bc->C * C->y;
	out->z = bc->A * A->z + bc->B * B->z + bc->C * C->z;
	return out;
}

Vec4* ssrS_bcpvec4(Vec3* bc, Vec4* A, Vec4* B, Vec4* C, Vec4* out) {
	ssr_assert(bc && A && B && C && out);
	out->x = bc->A * A->x + bc->B * B->x + bc->C * C->x;
	out->y = bc->A * A->y + bc->B * B->y + bc->C * C->y;
	out->z = bc->A * A->z + bc->B * B->z + bc->C * C->z;
	out->w = bc->A * A->w + bc->B * B->w + bc->C * C->w;
	return out;
}

void ssrS_lerpnum(float t, float* A, float* B, float* out) {
	*out = lerp(*A, *B, t);
}

void ssrS_lerpcolor(float t, Color A, Color B, Color* out) {
	*out = ssr_color(
		lerp(COLOR_R(A), COLOR_R(B), t),
		lerp(COLOR_G(A), COLOR_G(B), t),
		lerp(COLOR_B(A), COLOR_B(B), t),
		lerp(COLOR_A(A), COLOR_A(B), t)
	);
}

void ssrS_lerpvec2(float t, Vec2* A, Vec2* B, Vec2* out) {
	out->x = lerp(A->x, B->x, t);
	out->y = lerp(A->y, B->y, t);
}

void ssrS_lerpvec3(float t, Vec3* A, Vec3* B, Vec3* out) {
	out->x = lerp(A->x, B->x, t);
	out->y = lerp(A->y, B->y, t);
	out->z = lerp(A->z, B->z, t);
}

void ssrS_lerpvec4(float t, Vec4* A, Vec4* B, Vec4* out) {
	out->x = lerp(A->x, B->x, t);
	out->y = lerp(A->y, B->y, t);
	out->z = lerp(A->z, B->z, t);
	out->w = lerp(A->w, B->w, t);
}

static Color32 _out_color[RENDER_TARGET_COUNT];

Color32* out_color[RENDER_TARGET_COUNT] = {
	&_out_color[0],
	&_out_color[1],
	&_out_color[2],
	&_out_color[3],
	&_out_color[4],
	&_out_color[5],
};